1. Field of the Invention
The present invention generally relates to output driver circuits in a semiconductor device and, more particularly, to an output driver circuit provided in a 3V device and enabling connection between a 3V device and a 5V device.
2. Description of the Related Art
Recently, 3V devices and 5V devices coexist in some semiconductor devices. In such a case, an output driver connectable with both types of devices is used.
An output driver circuit for a 3V device may be composed of a pMOS transistor and an nMOS transistor. The drain of the pMOS transistor and the drain of the nMOS transistor are both connected to an input/output terminal. The input/output terminal is connected to a data bus. In such a construction, when a 5V signal arrives via the data bus, the 5V signal applies a forward voltage to a PN junction between the drain of the pull-up pMOS transistor and the n-well thereof, resulting in a leak current flowing in the junction.
FIGS. 1 and 2 show examples according to the related art for resolving the problem of leak current.
An output driver circuit of FIG. 1 comprises an output buffer 1, a step-up circuit 2, a pull-up nMOS transistor 3 and a pull-down nMOS transistor 4 connected in series. The source of the nMOS transistor 3 and the drain of the nMOS transistor 4 are connected to an input/output (I/O) terminal 5. The I/O terminal 5 is connected to a data bus.
The output buffer 1 receives an output enable signal /OE and data. The output buffer 1 outputs a signal for driving the step-up circuit 2 to a DPU node and supplies a voltage to be applied to the gate of the nMOS transistor 4, to a DPD node. The step-up circuit 2 controls the nMOS transistor 3 by outputting a voltage to be applied to the gate of the pull-up nMOS transistor 3, to a VPUMP node. More specifically, in a stand-by mode, a prime voltage VSS is applied to the gate of the pull-up nMOS transistor 3 and the gate of the pull-down nMOS transistor 4. When high data is to be output, the voltage VSS is raised to VCC and further stepped up to a voltage sufficiently high to turn on the nMOS transistor 3. In this way, a voltage drop in the nMOS transistor 3 is prevented so that the voltage VCC is properly output via the data bus.
When low data is to be output, the voltage output to the DPD node causes the pull-down nMOS transistor 4 to be turned on so that the voltage on the data bus is pulled down to the ground potential. In this state, the pull-up nMOS transistor 3 is turned off.
When high data is to be output, the pull-up nMOS transistor 3 is turned on by receiving the step-up voltage via the VPUMP. As a result, the I/O terminal 5 is connected to the predetermined voltage VCC. Accordingly, the voltage of the data bus is pulled up to VCC. In this state, the pull-down nMOS transistor 4 is turned off.
Since the nMOS transistor 3 in FIG. 1 is an nMOS transistor, it has a p-well instead of an n-well. Accordingly, the problem of leak current is avoided.
FIG. 2 shows another construction according to the related art for implementing 3V/5V tolerant input/output.
An nMOS transistor 14 is provided between a pull-up pMOS transistor 13 and a input/output terminal 16 of an output driver. An output buffer 11 receives an output enable signal /OE and data. The output buffer 11 controls the pull-up pMOS transistor 13 by outputting a voltage to be applied to the gate of the pull-up pMOS transistor 13, to a DPU node, and also controls the pull-down nMOS transistor 15 by outputting a voltage to be applied to the gate of the pull-down nMOS transistor 15. The step-up circuit 12 continually applies a sum of the voltage VCC and a threshold voltage Vth to the gate of the nMOS transistor 14. With this, when a 5V signal arrives via the data bus in a stand-by mode, the voltages at the gate and the drain of the nMOS transistor 14 cancel each other. Accordingly, the drain of the pull-up pMOS transistor 13 is not supplied with a voltage high enough to cause a leak current to flow.
In the construction of FIG. 1, 3V/5V tolerant I/O is implemented by preventing a leak current from flowing when a 5V signal arrives in a 3V device and by stepping up the gate voltage of the pull-up nMOS transistor when high data is to be read out. However, such an arrangement for reading out high data requires raising the gate voltage of the pull-up nMOS transistor 3 to VCC and then to the step-up voltage. As a result, a step-like output waveform is produced and access is slowed down. If an operation of raising the voltage from VSS to VCC and then raising the voltage VCC to a step-up voltage is performed in a short period of time in an attempt to prevent access from being slowed down, an excessive variation in the current results so that noise may be produced.
In the construction of FIG. 2, since the gate of the nMOS transistor 14 is continually maintained at VCC+Vth current consumption in a stand-by mode is relatively large. Further, since the gate of the nMOS transistor 14 is pulled up only to the level of VCC+Vth, the size of the nMOS transistor 14 should be relatively large in order to obtain a reduced access time.